The coefficient of thermal expansion (CTE) is one of the most critical reliability parameters for IC substrates, directly influencing solder joint fatigue, warpage behavior, and interfacial delamination in advanced semiconductor packages. This article provides a comprehensive method analysis of CTE testing for IC package substrates, covering material types, measurement principles, industry standards, and practical applications. Engineers involved in substrate design, materials qualification, and package reliability engineering will find actionable guidance on selecting the appropriate CTE characterization technique.
Technical Overview
An IC substrate, also known as a package substrate, serves as the crucial interconnect bridge between a semiconductor die and the printed circuit board (PCB). It redistributes the fine-pitch I/O of the chip to the coarser ball grid array (BGA) footprint while providing electrical connection, mechanical support, and thermal dissipation paths. As semiconductor packaging advances toward flip-chip BGA, chip-scale packaging, fan-out wafer-level packaging, and 2.5D/3D architectures, the dimensional stability of the substrate across operating and processing temperature ranges has become a dominant factor in package reliability.
The coefficient of thermal expansion (CTE) quantifies the fractional dimensional change of a material per degree of temperature change, typically expressed in parts per million per degree Celsius (ppm/°C). In an IC package, multiple materials with dissimilar CTE values are joined together: silicon (approximately 2.6 ppm/°C), copper (approximately 17 ppm/°C), solder, substrate laminate, and molding compound. When temperature cycles occur during reflow, burn-in, or field operation, CTE mismatches generate thermomechanical stresses at material interfaces. These stresses drive solder joint fatigue cracking, interfacial delamination, copper trace cracking, and excessive package warpage.
IC substrates are anisotropic materials, meaning their CTE differs along the in-plane directions (X and Y) and the out-of-plane direction (Z). In-plane CTE is governed primarily by the reinforcement system, such as glass cloth or core construction, while out-of-plane CTE depends mainly on the resin matrix and is typically two to four times higher. Below the glass transition temperature (Tg), the resin is in a glassy state with relatively low CTE; above Tg, the resin enters a rubbery state and the CTE can increase dramatically, sometimes exceeding 100 ppm/°C. Accurate characterization of all three axes, both below and above Tg, is therefore essential for substrate qualification and finite element simulation inputs.
Testing Samples
Bismaleimide Triazine (BT) Resin Substrates
BT resin substrates based on bismaleimide triazine chemistry reinforced with glass fabric are widely used in memory packaging, CSP, and traditional lead-frame replacement applications. They offer moderate Tg values between 180°C and 220°C and in-plane CTE values typically ranging from 10 to 17 ppm/°C, which can be tuned by glass cloth selection to approximate the CTE of the attached die or board. Test coupons preparation requires attention to panel orientation because the woven glass reinforcement introduces slight differences between the warp and weft (X and Y) directions.
Ajinomoto Build-up Film (ABF) Substrates
ABF-based substrates use a glass-fabric-free epoxy dielectric film laminated over a core to enable fine-line circuit formation for flip-chip and high-density packaging. The build-up layers exhibit resin-dominated CTE behavior, with in-plane CTE often between 20 and 40 ppm/°C below Tg and significantly higher values above Tg. Because ABF substrates are the mainstream solution for CPU, GPU, and ASIC packages, precise CTE profiling across the full reflow temperature range up to 260°C is critical for warpage prediction and solder joint reliability modeling.
FR-4 and Modified Epoxy Substrates
Standard and modified epoxy-glass substrates appear in lower-cost consumer and peripheral applications. Their CTE characteristics resemble conventional PCB laminates, with in-plane CTE of 12 to 16 ppm/°C and out-of-plane values frequently exceeding 50 ppm/°C below Tg. Sample preparation follows established laminate testing practices, and results are strongly influenced by resin content and glass style.
Ceramic Substrates
Ceramic substrates, including alumina (Al2O3), aluminum nitride (AlN), and low-temperature co-fired ceramic (LTCC), serve high-power, high-frequency, and hermetic packaging applications. Alumina exhibits a CTE near 6 to 7 ppm/°C, while aluminum nitride is approximately 4 to 5 ppm/°C, providing closer match to silicon. Ceramic materials display linear expansion behavior without a Tg transition, simplifying measurement but requiring high-temperature instrumentation due to processing and operating environments that may exceed 300°C.
Glass Core and Silicon Interposer Samples
Emerging glass-core substrates and silicon interposers for 2.5D integration provide CTE values of approximately 3 to 9 ppm/°C, closely matching silicon. These rigid, low-CTE materials are investigated to reduce warpage in large-body packages. Their low expansion magnitude demands high-resolution measurement systems because the absolute dimensional change over a practical temperature span is very small.
Multilayer Finished Substrate Coupons
Beyond raw laminate materials, finished multilayer substrates with patterned copper, plated through-holes, via arrays, and solder mask should be evaluated because copper distribution and layer stack-up alter the effective CTE of the composite structure. Coupons are typically cut to specified dimensions, conditioned at standard laboratory atmosphere (23°C, 50% relative humidity) for a minimum of 24 hours, and dried when moisture effects must be excluded.
Testing Items
A complete CTE characterization program for IC substrates generally includes the following measurement items, each addressing a distinct reliability concern:
- In-plane CTE (alpha 1, X/Y direction below Tg): evaluates dimensional stability during normal operation and influences solder joint shear strain.
- In-plane CTE (alpha 2, X/Y direction above Tg): captures the rubbery-state expansion relevant to reflow and high-temperature processing excursions.
- Out-of-plane CTE (Z direction below Tg): governs via barrel stress, copper plating reliability, and thickness change effects.
- Out-of-plane CTE (Z direction above Tg): critical for predicting blistering, delamination, and pressure-induced defects during lamination and reflow.
- Glass transition temperature (Tg): determined from the CTE slope inflection point; defines the boundary between alpha 1 and alpha 2 regions.
- Percent expansion at reflow temperature: total dimensional change at 245°C to 260°C, used directly in warpage simulation.
- Anisotropy ratio: comparison of Z-axis to in-plane CTE, an indicator of resin content and reinforcement quality.
- CTE hysteresis between heating and cooling cycles: reveals residual stress, moisture effects, and thermal aging behavior.
Testing Methods
Thermomechanical Analysis (TMA)
TMA is the industry-standard technique for substrate CTE measurement and is specified in IPC-TM-650 method 2.4.24 and ASTM E831. A sample, typically 3 to 6 mm square and 0.3 to 1.6 mm thick, is placed on a quartz platform with a low-mass quartz probe applying a static force of a few millinewtons to a few grams. The furnace ramps temperature at a controlled rate, commonly 5°C to 10°C per minute, across the range of interest, for example 30°C to 260°C for lead-free reflow compatibility.
The instrument records dimensional change with a linear variable differential transformer (LVDT) capable of sub-micron resolution, and CTE is computed as the slope of the expansion curve divided by initial length. For out-of-plane (Z) CTE, the sample is tested in the thickness direction as-cut. For in-plane (X/Y) CTE, the sample is prepared as an edge-oriented specimen so the expansion probe contacts the in-plane cross-section, or a dedicated in-plane TMA configuration is used. TMA simultaneously yields Tg from the intersection of the alpha 1 and alpha 2 regression lines. Key practices include purging with nitrogen or helium, applying minimal probe force to avoid sample indentation, and performing at least two runs to confirm the absence of thermal history effects.
Horizontal Dilatometry (ASTM E228)
Push-rod dilatometry measures expansion of larger rod or strip samples, typically 25 mm in length, positioned horizontally inside a furnace with a calibrated push rod transmitting displacement to a sensing transducer. The longer gauge length improves CTE resolution, making dilatometry well suited for in-plane measurements of glass cores, ceramic plates, and low-expansion materials where expansion over 100°C may amount to only a few micrometers. Corrections for the expansion of the reference holder and push rod are applied using a certified reference material such as fused silica, sapphire, or NIST standard reference materials.
Strain Gauge Method
Foil strain gauges bonded to substrate coupons measure apparent strain as temperature sweeps; after compensating for the gauge factor and gauge alloy expansion, the specimen CTE is extracted. This method accommodates large, full-size substrate panels and can map CTE at multiple locations to evaluate panel-level uniformity, which is valuable for detecting lot-to-lot glass cloth or resin variations. Careful adhesive selection and cure are required to ensure strain transfer integrity at elevated temperature, and the practical upper temperature limit is typically constrained to 150°C to 200°C.
Digital Image Correlation (DIC) and Optical Methods
Non-contact optical techniques, including DIC and high-temperature video extensometry, track a stochastic speckle pattern or fiducial marks on the substrate surface while the sample is heated on a hot stage or in an environmental chamber. Full-field displacement maps reveal local CTE variations around copper-dense regions, via fields, and pattern edges, which localized probe methods cannot capture. DIC is increasingly used for warpage-related studies because it measures the effective CTE of the finished composite substrate rather than the neat laminate.
X-Ray Diffraction Lattice Parameter Method
For crystalline ceramic substrates, precision lattice parameter measurement by X-ray diffraction as a function of temperature provides an ultrahigh-accuracy CTE reference, often used for material certification. The technique measures average bulk expansion of the crystallographic lattice and requires specialized high-temperature attachments, so its role in routine substrate qualification is limited to baseline material characterization.
Interpretation and Data Analysis
Regardless of method, the expansion curve is analyzed by segmenting the linear region below Tg (alpha 1), locating the inflection associated with Tg, and fitting the post-Tg linear region (alpha 2). The secant CTE referenced to a baseline temperature, often 25°C or 30°C, is reported when total expansion at a specific temperature is needed for simulation. Acceptance criteria commonly require in-plane CTE matching within a defined window of the silicon or PCB CTE, for example 10 to 16 ppm/°C, and out-of-plane CTE below a maximum threshold, frequently 50 ppm/°C below Tg, depending on the package architecture and customer specification.
Applications
CTE test data for IC substrates support a broad spectrum of engineering activities across the semiconductor packaging value chain:
- Substrate material qualification and supplier comparison during new package development, ensuring laminate and build-up films meet CTE and Tg specifications.
- Thermomechanical simulation inputs for warpage prediction of flip-chip BGA, LGA, and large-body packages during reflow and operation.
- Solder joint fatigue life assessment in temperature cycling reliability studies, where CTE mismatch between substrate, die, and board drives inelastic strain in joints.
- Stack-up design optimization, balancing core, prepreg, ABF, and copper layers to engineer an effective package CTE that minimizes stress.
- Failure analysis support, comparing CTE of failed units against known-good baselines to identify resin degradation, thermal aging, or material substitution.
- Process window definition for lamination, curing, and multiple reflow exposures, where alpha 2 behavior determines stress margins above Tg.
- Advanced packaging development, including glass-core substrates, silicon interposers, embedded die, and fan-out panel-level packaging where CTE matching is a primary design criterion.
- Automotive and high-reliability electronics qualification under AEC-Q100 and similar frameworks requiring validated CTE stability over extended thermal aging.
FAQ
Q: Why is the Z-axis CTE of an IC substrate so much higher than the in-plane CTE?
The woven glass fabric or rigid core constrains expansion in the X and Y directions, while the resin matrix can expand freely through the thickness. As a result, out-of-plane CTE is resin-dominated and commonly two to four times the in-plane value, with an even larger ratio above Tg.
Q: What temperature range should be used for CTE testing?
The range must bracket the actual thermal excursions of the package. For lead-free applications, 30°C to 260°C covers both operation and peak reflow. For ceramic or high-temperature substrates, extended ranges up to 300°C or beyond are appropriate. Both alpha 1 and alpha 2 should be reported whenever the range crosses Tg.
Q: Which standard governs substrate CTE measurement?
IPC-TM-650 method 2.4.24 is the primary industry standard for PCB and substrate laminate CTE by TMA, complemented by ASTM E831 for TMA in general and ASTM E228 for dilatometry. ISO 11359 provides parallel international guidance for thermomechanical analysis of plastics.
Q: How does moisture affect CTE test results?
Moisture plasticizes epoxy and ABF resins, shifting Tg downward and altering apparent expansion. Specimens should be conditioned consistently, and when dry-state properties are required, a pre-bake, such as 105°C for 2 hours followed by desiccated cooling, should be performed before testing.
Q: Why do first and second heating runs sometimes give different CTE values?
The first heating relieves residual stresses from lamination and patterning and may expel volatiles or moisture, causing a shifted or hysteretic expansion curve. Running a second thermal cycle after cooling confirms stabilized values, and the second run is frequently the reported result per internal laboratory protocols.
Q: Can TMA measure the effective CTE of a finished multilayer substrate?
Yes. Testing coupons cut from finished substrates captures the composite effect of copper balance, via density, and solder mask. However, heavily copper-loaded areas may show suppressed expansion, so sampling location should be documented, and DIC methods are recommended when full-field uniformity information is needed.